How to improve the RISC-V specification
My main project is to create an executable spec of the Intel Architecture
but, every now and then, I get to take a broader look at ISA specifications
and think about the strengths and weaknesses of other ISA specs:
what makes them work well; and what techniques they could borrow
from other specifications.
Earlier this month, someone asked me for my thoughts on the RISC-V
specification and I thought that it would be useful to share
what I found out.