RISC-V is an instruction set architecture.
RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
— RISCV.org
Notes related to RISC-V architecture
CHERI-Flute, Instruction set architecture
Papers related to RISC-V architecture
- ISA semantics for ARMv8-A, RISC-V, and CHERI-MIPS [armstrong:popl19:2019]
- The state of Sail [armstrong:spisa:2019]
- End-to-end formal verification of a RISC-V processor extended with capability pointers [gao:fmcad:2021]
- Pydgin: generating fast instruction set simulators from simple architecture descriptions with meta-tracing JIT compilers [lockhart:ispass:2015]
- Scaling symbolic evaluation for automated verification of systems code with Serval [nelson:sosp:2019]
- A new verified compiler backend for CakeML [tan:icfp:2016]
- Raising binaries to LLVM IR with MCTOLL (WIP paper) [yadavalli:lctes:2019]