Power-PC architecture

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Notes: instruction set architecture

Power-PC is an instruction set architecture.

Capstone disassembler, Instruction set architecture, Sail ISA specification language

  • Mixed-size concurrency: ARM, POWER, C/C++11, and SC [flur:popl:2017]
  • An integrated concurrency and core-ISA architectural envelope definition, and test oracle, for IBM POWER multiprocessors [gray:micro:2015]
  • Verified LISP Implementations on ARM, x86 and PowerPC [myreen:tphols:2009]
  • Understanding POWER multiprocessors [sarkar:pldi:2011]