Mixed-size concurrency: ARM, POWER, C/C++11, and SC
Shaked Flur, Susmit Sarkar, Christopher Pulte, Kyndylan Nienhuis, Luc Maranget, Kathryn E. Gray, Ali Sezgin, Mark Batty, Peter Sewell[doi] [ISBN] [Google Scholar] [DBLP] [Citeseer] [url]
Proceedings of the 44th ACM SIGPLAN Symposium on Principles of Programming Languages
POPL 2017
Paris, France
Association for Computing Machinery
New York, NY, USA
Pages 429-442
2017
Note(s): ISA specification, instruction set architecture, Arm architecture, PowerPC architecture
POPL 2017
Paris, France
Association for Computing Machinery
New York, NY, USA
Pages 429-442
2017
Note(s): ISA specification, instruction set architecture, Arm architecture, PowerPC architecture