Simplifying ARM concurrency: Multicopy-atomic axiomatic and operational models for ARMv8

Christopher Pulte, Shaked Flur, Will Deacon, Jon French, Susmit Sarkar, Peter Sewell
[doi] [Google Scholar] [DBLP] [Citeseer] [url]

Proc. ACM Program. Lang. 2(POPL)
Association for Computing Machinery
New York, NY, USA
dec 2017
Note(s): Arm architecture, weak memory, ISA specification