GeST: An automatic framework for generating CPU stress-tests

Zacharias Hadjilambrou, Shidhartha Das, Paul N Whatmough, David Bull, Yiannakis Sazeides
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Read: 21 September 2021

2019 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)
Pages 1-10
Note(s): power virus, resonant frequency, Arm architecture, x86 architecture, hardware faults, genetic algorithm

Digital electronics is a myth: the underlying analog nature of digital electronics is revealed by overclocking, voltage droops, resonance and a host of other effects. Designers (and users) find it useful to stress-test CPUs using power viruses that try to create high IPC load, thermal load, voltage noise, etc. at the resonant frequency of the chips power delivery network (PDN). (Matching the PDN’s 1st order resonance frequency maximizes the CPU voltage droops and overshoots.)

The paper cites around 10 other papers about these various forms of virus. Early power viruses were hand-written, then created using genetic algorithms, some use simulators to evaluate different sequences, some use real hardware, some use measurements like IPC as proxies for power or temperature, and various work focused on different kinds of virus (power, voltage noise).

GeST is an open source, easy to use framework that uses genetic algorithms to generate a range of different viruses using whatever measurement you want to use in the feedback mechanism, using whatever fitness function you want, and supporting whatever assembly language you want to use.

GeST is demonstrated for both Arm and AMD processors to create IPC, power, thermal and voltage noise viruses and the differences between the solutions for the different feedback mechanisms are discussed.