An integrated concurrency and core-ISA architectural envelope definition, and test oracle, for IBM POWER multiprocessors

Kathryn E. Gray, Gabriel Kerneis, Dominic P. Mulligan, Christopher Pulte, Susmit Sarkar, Peter Sewell
[doi] [Google Scholar] [DBLP] [Citeseer]

MICRO 2015: Proceedings of the 48th International Symposium on Microarchitecture (MICRO 2015)
Waikiki, Hawaii, USA
Pages 635-646
December 2015
Note(s): PowerPC architecture, ISA specification, instruction set architecture